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-- Company: 
-- Engineer: 
-- 
-- Create Date:    21:30:59 04/10/2010 
-- Design Name: 
-- Module Name:    ClkDiv - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ClkDiv is
    Port ( clkin : in  STD_LOGIC;
				reset : in STD_LOGIC;
           clkout : out  STD_LOGIC);
end ClkDiv;

architecture Behavioral of ClkDiv is
	constant div : INTEGER := 50;
begin
	PROCESS (clkin, reset)
		VARIABLE cnt : INTEGER range 0 to div;
	BEGIN
		IF reset = '1' THEN
			cnt := 0;
		ELSIF rising_edge(clkin) THEN
			IF (cnt = div) THEN
				cnt := 0;
				clkout <= '1';
			ELSE
				cnt := cnt + 1;
				clkout <='0';
			END IF;
		END IF;
	END PROCESS;

end Behavioral;

